The majority of present day integrated circuits (ICs) are implemented by using a plurality of interconnected field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs or MOS transistors). An MOS transistor includes a gate electrode as a control electrode that is formed on a semiconductor substrate and spaced-apart source and drain regions formed within the semiconductor substrate and between which a current can flow. A control voltage applied to the gate electrode controls the flow of current through a channel in the semiconductor substrate between the source and drain regions. The ICs are usually formed using both P-channel FETs (PMOS transistors) and N-channel FETs (NMOS transistors) and the IC is then referred to as a complementary MOS or CMOS integrated circuit (IC).
There is a continuing trend to incorporate more and more circuitry on a single IC chip. To incorporate the increasing amount of circuitry, the size of each individual device in the circuit and the size and spacing between device elements (the feature size) must decrease. The individual elements of the circuits, that is, MOS transistors and other passive and active circuit elements, must be interconnected by metal or other conductors to implement the desired circuit function. Some small resistance is associated with each contact between the conductor and the circuit element. As the feature size decreases, the contact resistance increases and becomes a greater and greater percentage of the total circuit resistance. As feature sizes decrease from 150 nanometer (nm) to 90 nm, then to 45 nm and below the contact resistance becomes more and more important. At feature sizes of 32 nm, the contact resistance likely will dominate chip performance unless some innovation changes the present trend.
One solution for lowering contact resistance is to fabricate CMOS integrated circuits utilizing dual silicides, that is, different silicides for contact to the PMOS transistor and for contact to the NMOS transistor. In this regard, metal suicides that will exhibit lower potential barrier heights with respect to the doped semiconductor substrate can be used. Lower potential barrier height between a silicide and the doped semiconductor substrate results in lower contact resistance, which in turn results in lower total external resistance of the CMOS, and hence improved device performance. However, conventional methods for fabricating a CMOS integrated circuit using dual silicides requires forming the higher temperature silicide first, followed by forming the low temperature silicide. Protecting some transistors (and other devices) from silicidation while siliciding other transistors significantly complicates the fabrication process and may cause generation of various defects.
Accordingly, it is desirable to provide improved methods for fabricating CMOS integrated circuits that utilize different metal silicides for PMOS and NMOS transistors. In addition, it is desirable to provide methods for fabricating low contact resistance CMOS integrated circuits that reduce processing steps. It also is desirable to provide methods for fabricating low contact resistance CMOS integrated circuits that reduce defect generation during silicidation. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.